The present invention relates to a method and apparatus for decoding input symbols representing words including a plurality of information bits. The invention has particular application to the decoding of encoded symbols which have been subjected to phase shift key (PSK) modulation. The invention is advantageously employed in decoding phase shift key modulated signals for digital television signal reception.
Recently, a new class of error-control codes, termed xe2x80x9cturbo-codesxe2x80x9d, has been introduced. These codes provide error performance close to the Shannon limit by using an iterative decoding technique that relies upon simple constituent codes. A natural extension to improve the bandwidth efficiency of turbo-codes is to apply them to trellis coded modulation (TCM) and pragmatic trellis coded modulation (PCTM) systems.
In a known modulation system, a turbo-encoder encodes a serial stream of input data bits at a rate R of 1/3 to produce two parity bits in parallel with each input data bit. The information and parity bits are subject to demultiplexing in a demultiplexer so as to form symbols each of which includes a number of information bits and a number of parity bits. The parity bits are punctured in a puncturing module so as to reduce the number of parity bits and thereby increase the data rate of the system. The bits of each symbol are interleaved in an interleaver and passed to a signal mapping module. The output from the mapping module comprises the I and Q components necessary for input to a PSK modulator.
One of the serious drawbacks associated with the application of turbo-codes is the effect of xe2x80x9cflattening error degradationxe2x80x9d by which is meant the effect whereby the bit error ratio at the output of the turbo-decoder cannot be reduced below certain values which depend on the type of turbo-code and are in the range of 10xe2x88x928 to 10xe2x88x929. Although this figure is acceptable for most applications, digital television broadcasting requires quasi-error free performance in which the bit error ratio is 10xe2x88x9211. In order to meet this requirement, the conventional solution has been the serial concatenation of the Reed Solomon code and a binary turbo-code. However, the concatenated technique is not bandwidth efficient as the turbo-codes are not associated with any trellis coded modulation. Furthermore this technique has not used the full error correction power of the concatenated scheme because it has relied on hard decision information from the turbo-decoder.
It is one aim of the present invention to achieve the desired data rate whilst improving the bit-error ratio.
According to the present invention, there is now provided decoder apparatus to decode symbols each representing a digital wording comprising a turbo encoded bit, a parity bit and at least one uncoded bit, the apparatus comprising: a first soft metric generator to produce a soft metric of the encoded bit in each symbol; one or more second soft metric generators to generate a soft metric of the uncoded bit in each symbol; a turbo decoder to decode the soft metric of the encoded bit so as to produce a hard value and a soft estimate of the encoded bit; a turbo encoder to encode the hard value of the encoded bit to produce a reconstruction of the encoded bit and two parity bits; a puncture module to puncture the parity bits once; and, one or more hard decision modules to produce a hard decision for the uncoded bit of each symbol.
Further according to the present invention, there is provided a method of decoding symbols each representing a digital word comprising a turbo encoded bit, a parity bit and at least one uncoded bit the method comprising the steps of: producing a soft metric of the encoded bit in each symbol; generating a soft metric of the uncoded bit in each symbol; employing a turbo-decoder to decode the soft metric of the encoded bit so as to produce a hard value and a soft estimate of the encoded bit; employing a turbo encoder to encode the hard value of the encoded bit to produce a reconstruction of the encoded bit and two parity bits, puncturing the parity bits once; and, producing a hard decision for the uncoded bit of each symbol.